DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 34
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 34 of 1154
- Download datasheet (32Mb)
1–20
Figure 1–5. Stratix IV GT Device Packaging Ordering Information
Document Revision History
Table 1–10. Document Revision History (Part 1 of 2)
Stratix IV Device Handbook Volume 1
February 2011
March 2010
November 2009
F: FineLine BGA (FBGA)
H: Hybrid FineLine BGA
Package Type
Date
2 = 230k LEs
3 = 290k LEs
4 = 360k LEs
5 = 530k LEs
Family S i g n a t u r e
Aggregate Bandwidth
Device Density
Version
Figure 1–5
Table 1–10
3.0
3.2
3.1
EP4S
40G
100G
EP4S
■
■
■
■
■
■
■
■
■
■
■
■
■
40G
Updated
Applied new template.
Minor text edits.
Updated Table 1–1, Table 1–2, and Table 1–7.
Updated Figure 1–3.
Updated the “Stratix IV GT Devices” section.
Added two new references to the Introduction section.
Minor text edits.
Updated the “Stratix IV Device Family Overview”, “Feature Summary”, “Stratix IV GT
Devices”, “High-Speed Transceiver Features”, “FPGA Fabric and I/O Features”, “Highest
Aggregate Data Bandwidth”, “System Integration”, and “Integrated Software Platform”
sections.
Added Table 1–3, Table 1–6, and Table 1–9.
Updated Table 1–1, Table 1–2, Table 1–4, Table 1–5, Table 1–7, and Table 1–8.
Updated Figure 1–3, Figure 1–4, and Figure 1–5.
Minor text edits.
shows the ordering codes for Stratix IV GT devices.
lists the revision history for this chapter.
230
2
Table 1–7
F
Corresponds to pin count
40 = 1517 pins
45 = 1932 pins
Ball Array Dimension
40
and
Table
C
1–8.
2
Changes
ES
Chapter 1: Overview for the Stratix IV Device Family
ES: Engineering sample
Indicates specific device options
N: Lead-free devices
1, 2, 3 with 1 being the fastest
C: Commercial temperature (t
I :
Operating Temperature
Speed Grade
Optional Suffix
Industrial temperature (t
February 2011 Altera Corporation
Document Revision History
J
= 0°C to 100°C)
J
= 0 C to 85 C)
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