DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 916

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–70
Figure 5–36. Connecting ALTGX and ALTGX_RECONFIG Instances with EyeQ Enabled
Stratix IV Device Handbook Volume 2: Transceivers
reconfig_mode_sel[3:0]
ctrl_writedata[15:0]
ALTGX_RECONFIG Instance
ctrl_address[15:0]
EyeQ Control
Figure 5–36
instances and the EyeQ control logic in the dynamic reconfiguration controller.
Controlling the EyeQ Hardware
The EyeQ hardware is controlled by writing to the EyeQ registers using EyeQ
interface registers in the ALTGX_RECONFIG instance.
memory of the 16-bit EyeQ registers.
Table 5–13. EyeQ Register Mapping
0×0
0×1
Block
ctrl_readdata[15:0]
ctrl_write
Address
ctrl_waitrequest
ctrl_read
error
shows the connections between the EyeQ hardware in the ALTGX
busy
reconfig_fromgxb[17:0]
reconfig_togxb[3:0]
■
■
■
■
Bit[0]—0/1: Disable/Enable EyeQ feature
Bit [15:1]—15'b000000000000000
Bits [5:0]—EyeQ phase step value. Refer to
phase step encoding.
Bits [15:6]—10'b0000000000
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Receiver Channel 0
EyeQ Hardware
ALTGX Instance
Description
Dynamic Reconfiguration Modes Implementation
Table 5–13
February 2011 Altera Corporation
Table 5–14
lists the register
for the EyeQ
rx_datain[0]