DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 373
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 373 of 1154
- Download datasheet (32Mb)
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
JTAG Configuration
April 2011 Altera Corporation
f
f
1
You must connect the nCE pin to GND or drive it low during JTAG configuration. In
multi-device FPP, AS, and PS configuration chains, the first device’s nCE pin is
connected to GND, while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while its nCEO pin is
left floating. In addition, the CONF_DONE and nSTATUS signals are all shared in
multi-device FPP, AS, or PS configuration chains so the devices can enter user mode at
the same time after configuration is complete. When the CONF_DONE and nSTATUS
signals are shared among all the devices, you must configure every device when JTAG
configuration is performed.
If you only use JTAG configuration, Altera recommends connecting the circuitry as
shown in
so that each device can enter user mode individually.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the second device’s nCE pin, which prompts the
second device to begin configuration. Therefore, if these devices are also in a JTAG
chain, ensure the nCE pins are connected to GND during JTAG configuration or that
the devices are JTAG configured in the same order as the configuration chain. As long
as the devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO of the previous device drives the nCE of the next device
low when it has successfully been JTAG configured.
You can place other Altera devices that have JTAG support in the same JTAG chain for
device programming and configuration.
JTAG configuration support is enhanced and allows more than 17 Stratix IV devices to
be cascaded in a JTAG chain.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
You can configure Stratix IV devices using multiple configuration schemes on the
same board. Combining JTAG configuration with AS configuration on your board is
useful in the prototyping environment because it allows multiple methods to
configure your FPGA.
For more information about combining JTAG configuration with other configuration
schemes, refer to the
the Configuration Handbook.
Figure
10–17, where each of the CONF_DONE and nSTATUS signals are isolated,
Combining Different Configuration Schemes
Configuring Mixed Altera FPGA Chains
Stratix IV Device Handbook Volume 1
chapter in volume 2 of
chapter in
10–39
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