H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 11

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
13.4.4 Master
Receive Operation
Figure 13.14 Sample
Flowchart for
Operations in Master
Receive Mode
(Receiving a Single
Byte) (WAIT = 1)
13.4.5 Slave Receive
Operation
13.4.6 Slave Transmit
Operation
13.6 Usage Notes
Figure 13.34 ICDR
Read and ICCR
Access in Slave
Transmit Mode
Page
308
310
313
317
320
332
333,
334
335
336
336,
337
Revisions (See Manual for Details)
Figure 13.14 amended
Description amended
15. Clear the WAIT bit in ICMR to cancel the wait mode. ...
Description amended
3. ... The master device ... and transmit/receive direction (R/W),
in synchronization with the transmit clock pulses.
Description amended
3. ... The master device ... and transmit/receive direction (R/W),
in synchronization with the transmit clock pulses.
8. Confirm that the STOP bit is cleared to 0 and clear the IRIC
flag to 0.
Description amended
2. ... If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to
1, ...
8. Notes on start condition issuance for retransmission
Note amended
Note: This restriction on usage can be canceled by setting the
FNC1 and FNC0 bits to 11 in ICXR.
10. Notes on WAIT function
Description added
Figure 13.34 amended
(Before) R/W
13. Notes on TRS bit setting in slave mode
Note amended
Note: This restriction on usage can be canceled by setting the
FNC1 and FNC0 bits to 11 in ICXR.
14. Notes on Arbitration Lost in master mode
Description added
No
Read IRIC flag in ICCR
Set ACKB = 1 in ICSR
Read ICDR
IRIC = 1?
(After) R/W
Yes
Rev. 2.00 Mar 21, 2006 page xi of xxxviii
[2] Start receiving. The first read
[3] Wait for a receive wait
[7] Set acknowledge data for
is a dummy read.
(Set IRIC at the fall of the 8th clock)