H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 318

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 I
13.3.5
ICCR controls the I
Bit Bit Name
7
6
5
4
Rev. 2.00 Mar 21, 2006 page 280 of 518
REJ09B0299-0200
ICE
IEIC
MST
TRS
I
2
C Bus Control Register (ICCR)
2
C Bus Interface (IIC)
Initial Value R/W
0
0
0
0
2
C bus interface and performs interrupt flag confirmation.
R/W
R/W
R/W
R/W
Description
I
0: I
interface module internal state is initialized. SAR and SARX
can be accessed.
1: I
operation, and the ports function as the SCL and SDA
input/output pins. ICMR and ICDR can be accessed.
I
0: Disables interrupts from the I
1: Enables interrupts from the I
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they lose
in a bus contention in master mode with the I
In slave receive mode with I
the first frame immediately after the start condition sets
these bits in receive mode or transmit mode automatically
by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
2
2
C bus interface modules are stopped and I
C bus interface modules can perform transfer
2
C bus format, the R/W bit in
2
2
C bus interface to the CPU.
C bus interface to the CPU
2
C bus format.
2
C bus