H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 367

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6. The I
and 300 ns. The I
table 13.8. However, because of the rise and fall times, the I
not be satisfied at the maximum transfer rate. Table 13.10 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I
BUFO
SCLLO
fails to meet the I
in high-speed mode and t
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
STASO
in standard mode fail to satisfy the I
Sr
/t
Sf
. Possible solutions that should be investigated
Rev. 2.00 Mar 21, 2006 page 329 of 518
2
C bus interface specifications may
Section 13 I
2
C bus.
2
C bus interface
2
C Bus Interface (IIC)
2
C bus.
REJ09B0299-0200
cyc
, as shown in