H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 415

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
7
6
5
STR3 (TWRE = 1 or SELSTR3 = 0)
Bit Name Initial Value Slave Host Description
IBF3B
OBF3B
MWMF
0
0
0
R/(W) * R
R
R
R/W
R
R
Bidirectional Data Register Input Buffer Full
Set to 1 when the host processor writes to TWR15.
This is an internal interrupt source to the slave
processor (this LSI). IBF3B is cleared to 0 when the
slave processor reads TWR15.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR15 using I/O
write cycle
Bidirectional Data Register Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
TWR15. OBF3B is cleared to 0 when the host
processor reads TWR15.
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
OBF3B bit
1: [Setting condition]
When the slave processor writes to TWR15
Master Write Mode Flag
Set to 1 when the host processor writes to TWR0.
MWMF is cleared to 0 when the slave processor (this
LSI) reads TWR15.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR0 using I/O
write cycle while SWMF = 0
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 377 of 518
REJ09B0299-0200