H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 277

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse
of the basic clock, data is latched at the middle of each bit, as shown in figure 12.3. Thus the
reception margin in asynchronous mode is determined by formula (1) below.
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = (0.5 –
M = {0.5 – 1/(2 × 16)} × 100
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
}
M: Reception margin (%)
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode
2N
1
0
) –
8 clocks
Start bit
D – 0.5
N
16 clocks
(1 + F) – (L – 0.5) F } × 100
7
[%] = 46.875 %
Section 12 Serial Communication Interface (SCI)
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Rev. 2.00 Mar 21, 2006 page 239 of 518
D0
[%]
... Formula (1)
7
REJ09B0299-0200
15 0
D1