H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 354

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 I
Continuous Receive Operation:
Figure 13.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).
Rev. 2.00 Mar 21, 2006 page 316 of 518
REJ09B0299-0200
Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
2
C Bus Interface (IIC)
Read AASX, AAS and ADZ in ICSR
No
No
and TRS = 0 in ICCR
Set HNDS = 0 in ICXR
Set ACKB = 0 in ICSR
Set ACKB = 1 in ICSR
Slave receive mode
Read IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read TRS in ICCR
Wait for one frame
and ADZ = 1?
Set MST = 0
(n-2)th-byte
ICDRF = 1?
ESTP = 1 or
ICDRF = 1?
ICDRF = 1?
Read ICDR
Read ICDR
STOP = 1?
Read ICDR
reception?
IRIC = 1?
TRS = 1?
IRIC = 1?
AAS = 1
End
Yes
No
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
No
No
No
Yes
* n: Address + total number of bytes received
Slave transmit mode
[3] to [7] Wait for one byte to be received (slave address + R/W)
[10] Read the receive data. The first read is a dummy read.
[11] Wait for one byte to be received
[1] Select slave receive mode.
General call address processing
[9] Wait for ACKB setting and set acknowledge data
[12] Detect stop condition
[2] Read the receive data remaining unread.
[8] Clear IRIC
[13] Clear IRIC
[14] Read the last receive data
[15] Clear IRIC
(after the rise of the 9th clock of (n - 1)th byte data)
for the last reception
(Set IRIC at the rise of the 9th clock)
(Set IRIC at the rise of the 9th clock)
* Description omitted