H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 330

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 I
13.3.7
DDCSWR controls IIC internal latch clearance.
Bit Bit Name Initial Value R/W
7 to
5
4
3
2
1
0
Note: * This bit is always read as 1.
Rev. 2.00 Mar 21, 2006 page 292 of 518
REJ09B0299-0200
—
—
CLR3
CLR2
CLR1
CLR0
DDC Switch Register (DDCSWR)
2
C Bus Interface (IIC)
All 0
0
1
1
1
1
R/W
R
W *
W *
W *
W *
Description
Reserved
The initial value should not be changed.
Reserved
IIC Clear 3 to 0
Controls initialization of the internal state of IIC_0 and
IIC_1.
00--: Setting prohibited
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal latch cleared
0111: IIC_0 and IIC_1 internal latches cleared
1---: Invalid setting
When a write operation is performed on these bits, a clear
signal is generated for the internal latch circuit of the
corresponding module, and the internal state of the IIC
module is initialized.
These bits can only be written to; they are always read as
1. Write data to this bit is not retained.
To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not
use a bit manipulation instruction such as BCLR.
When clearing is required again, all the bits must be written
to in accordance with the setting.