H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 201

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however. In buffered input capture, if either set of two registers to which data
will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture
input signal arrives, input capture is delayed by one system clock ( ). Figure 9.10 shows the
timing when BUFEA = 1.
9.5.6
The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The
FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB,
ICRC, or ICRD). Figure 9.11 shows the timing of setting the ICFA to ICFD flag.
Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting
Timing of Input Capture Flag (ICF) Setting
φ
FTIA
Input capture
signal
φ
Input capture
signal
ICFA to ICFD
FRC
ICRA to ICRD
Figure 9.10 Buffered Input Capture Timing (BUFEA = 1)
CPU read cycle of ICRA or ICRC
T 1
T 2
Section 9 16-Bit Free-Running Timer (FRT)
Rev. 2.00 Mar 21, 2006 page 163 of 518
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