H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 324

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 13 I
Table 13.5 Flags and Transfer States (Slave Mode)
MST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Legend:
0:
1:
—:
Rev. 2.00 Mar 21, 2006 page 286 of 518
REJ09B0299-0200
TRS
0
0
1 /0 *
0
1 /0 *
1
1
1
1
1
1
0
0
0
0
0
0-state retained
1-state retained
Previous state retained
1
1
BBSY ESTP STOP IRTR
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
2
C Bus Interface (IIC)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 /0 *
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1 *
3
0
0
0
0
1
1 /0 *
1 /0 *
1 /0 *
1 /0 *
1
2
2
2
AASX AL
0
0
0
0
1
0
0
0
0
0
0
0
0
AAS
0
0
1
1
0
0
0
0
0
0
0
ADZ
0
0
0
1
0
0
0
0
0
0
0
0
0
0
ACKB ICDRF ICDRE State
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
Idle state (flag
clearing required)
Start condition
detected
SAR match in first
frame (SARX
General call address
match in first frame
(SARX
SARS match in first
frame (SAR
Transmission end
(ACKE = 1 and
ACKB = 1)
Transmission end
with ICDRE = 0
ICDR write with the
above state
Transmission end
with ICDRE = 1
ICDR write with the
above state
Automatic data
transfer from ICDRT
to ICDRS with the
above state
Reception end with
ICDRF = 0
ICDR read with the
above state
Reception end with
ICDRF = 1
ICDR read with the
above state
Automatic data
transfer from ICDRS
to ICDRR with the
above state
Stop condition
detected
H'00)
SARX)
SAR)

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