H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 65

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 2.1
Function
Data transfer
Arithmetic
operations
Logic operations
Shift
Bit manipulation
Branch
System control
Block data transfer EEPMOV
Legend:
B:
W: Word
L:
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
Byte
Longword
2. B
3. Cannot be used in this LSI.
4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5.
5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
STM/LDM instruction, because ER7 is the stack pointer.
CC
Instruction Classification
is the general name for conditional branch instructions.
Instructions
MOV
POP *
LDM *
MOVFPE *
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
TAS *
AND, OR, XOR, NOT
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
B
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
CC
*
2
, JMP, BSR, JSR, RTS
4
1
5
, PUSH *
, STM *
3
, MOVTPE *
5
1
3
Rev. 2.00 Mar 21, 2006 page 27 of 518
REJ09B0299-0200
Size
B/W/L
W/L
L
B
B/W/L
B
B/W/L
L
B/W
W/L
B
B/W/L
B/W/L
B
—
—
—
Section 2 CPU
Total: 65
Types
5
19
4
8
14
5
9
1