H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 13

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
17.8.1
Program/Program-
Verify
Figure 17.9
Program/Program-
Verify Flowchart
18.5 Subclock Input
Circuit
19.1.1 Standby
Control Register
(SBYCR)
19.1.1 Standby
Control Register
(SBYCR)
Table 19.1 Operating
Frequency and Wait
Time
20.1 Register
Addresses (Address
Order)
Page
426
438, 439
443
443
460
Revisions (See Manual for Details)
Figure 17.9 amended
Note 7: Write Pulse Width
Description of "When Subclock Is Not Needed" and "
Note on Subclock Usage" added
SCK2 to SCK0 description in bits 2 to 0 amended
When …, SCK2 to SCK0 must be cleared to B'00.
Table amended
Address in P7ODA amended
(Before) H'FE02
Note: Use a z3 s write pulse for additional programming.
STS2
0
Number of Writes n
Write pulse application subroutine
Wait (z1) s, (z2) s or (z3) s
1000
998
999
10
11
12
13
Clear PSU bit in FLMCR2
1
2
3
4
5
6
7
8
9
Reprogram data storage
Additional-programming
Sub-Routine Write Pulse
Set PSU bit in FLMCR2
Program data storage
Clear P bit in FLMCR1
Set P bit in FLMCR1
data storage area
area (128 bytes)
area (128 bytes)
0
STS1
(128 bytes)
WDT enable
Disable WDT
Wait (α) s
Wait (β) s
Wait (γ) s
RAM
End Sub
Write Time (z) s
STS0
0
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
*6
*6
*5
*6
*6
Wait Time
8192 states
*6
Increment address
(After) H'FE01
Rev. 2.00 Mar 21, 2006 page xiii of xxxviii
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
NG
Apply write pulse (Additional programming)
Transfer reprogram data to reprogram data area
Additional-programming data computation
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
data area and reprogram data area
H'FF dummy write to verify address
additional-programming data area
Apply
10 MH z 8 MHz
0.8
Clear SWE bit in FLMCR1
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
write pulse z1
End of programming
Read verify data
OK
OK
Wait (x) s
Wait (γ) s
Wait (ε) s
Write data =
Wait (η) s
Wait (θ) s
verify data?
OK
128-byte
START
m = 0 ?
m = 0
6 n ?
n = 1
6 n?
1.0
OK
OK
Sub-Routine-Call
s or z2 s
NG
NG
NG
6 MHz
1.3
*6
*6
*6
*
NG
*6
*6
*
*6
See Note 7 for pulse width
2
3
*
*
*
* 1
4
3
4
*
*
m = 1
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
4
Clear SWE bit in FLMCR1
4 MHz
2.0
Programming failure
s
Wait (θ) s
n
(N)?
OK
2 MHz
4.1
NG
n
n + 1
Unit
ms
*6