H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 99

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR after execution of trap instruction exception handling.
Table 4.3
Legend:
1:
—: Retains value prior to execution
4.6
Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Interrupt Control Mode
0
1
Set to 1
Stack Status after Exception Handling
Status of CCR after Trap Instruction Exception Handling
Note: Ignored on return.
SP
Figure 4.2 Stack Status after Exception Handling
Normal mode
(16 bits)
CCR*
CCR
PC
CCR
I
1
1
Rev. 2.00 Mar 21, 2006 page 61 of 518
SP
Advanced mode
Section 4 Exception Handling
(24 bits)
CCR
PC
UI
1
REJ09B0299-0200

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