H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 248

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Watchdog Timer (WDT)
11.3.2
TCSR selects the clock source to be input to TCNT, and the timer mode.
Rev. 2.00 Mar 21, 2006 page 210 of 518
REJ09B0299-0200
Bit
7
6
5
4
3
TCSR_0
Bit Name Initial Value R/W
OVF
WT/IT
TME
—
RST/NMI 0
Timer Control/Status Register (TCSR)
0
0
0
0
R/(W) *
R/W
R/W
R/(W)
R/W
1
Description
Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
Reserved
The initial value should not be changed.
Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
When TCSR is read when OVF = 1 *
written to OVF
When 0 is written to TME
2
, then 0 is