H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 464

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 ROM
8. The maximum number of repetitions of the program/program-verify sequence to the same bit
Rev. 2.00 Mar 21, 2006 page 426 of 518
REJ09B0299-0200
is (N).
Note 7: Write Pulse Width
Note: Use a z3 s write pulse for additional programming.
Number of Writes n
Write pulse application subroutine
Wait (z1) s, (z2) s or (z3) s
1000
998
999
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if
10
11
12
13
Clear PSU bit in FLMCR2
Reprogram data storage
Additional-programming
1
2
3
4
5
6
7
8
9
Sub-Routine Write Pulse
Reprogram Data Computation Table
Set PSU bit in FLMCR2
Program data storage
Clear P bit in FLMCR1
Set P bit in FLMCR1
data storage area
Original Data
area (128 bytes)
area (128 bytes)
(128 bytes)
WDT enable
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of z1 s or z2 s is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of
6. The values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N are shown in section 21.1.4, Flash Memory Characteristics.
Disable WDT
Wait (α) s
Wait (γ) s
Wait (β) s
(D)
RAM
End Sub
0
0
1
1
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
additional-programming data is executed, a z3 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Write Time (z) s
Figure 17.9 Program/Program-Verify Flowchart
Verify Data
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
(V)
0
1
0
1
*6
Reprogram Data
*6
*5
*6
*6
*6
(X)
Increment address
1
0
1
1
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
NG
Comments
Apply write pulse (Additional programming)
Transfer reprogram data to reprogram data area
Additional-programming data computation
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Apply
Clear SWE bit in FLMCR1
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
write pulse z1
End of programming
Read verify data
OK
Wait (η) s
OK
Wait (x) s
Wait (γ) s
Wait (ε) s
Write data =
verify data?
Wait (θ) s
OK
128-byte
START
m = 0 ?
6 n ?
m = 0
6 n?
n = 1
Additional-Programming Data Computation Table
Reprogram Data
OK
OK
Sub-Routine-Call
s or z2 s
(X')
0
0
1
1
NG
NG
NG
Verify Data
*6
*6
*6
*
NG
*6
*6
*6
*
(V)
See Note 7 for pulse width
2
0
1
0
1
3
*
*
* 1
*
3
4
4
*
*
m = 1
4
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Clear SWE bit in FLMCR1
Programming Data (Y)
Programming failure
s
Additional-
Wait (θ) s
n
0
1
1
1
(N)?
OK
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
NG
n
Comments
n + 1
*6