H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 31

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 13.12 Example of Stop Condition Issuance Operation Timing in Master
Figure 13.13 Sample Flowchart for Operations in Master Receive Mode
Figure 13.14 Sample Flowchart for Operations in Master Receive Mode
Figure 13.15 Example of Master Receive Mode Operation Timing
Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode
Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1).............. 312
Figure 13.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS = 1). 314
Figure 13.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS = 1). 315
Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0).............. 316
Figure 13.21 Example of Slave Receive Mode Operation Timing (1)
Figure 13.22 Example of Slave Receive Mode Operation Timing (2)
Figure 13.23 Sample Flowchart for Slave Transmit Mode ....................................................... 319
Figure 13.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) ........................ 321
Figure 13.25 IRIC Setting Timing and SCL Control (1)........................................................... 322
Figure 13.26 IRIC Setting Timing and SCL Control (2)........................................................... 323
Figure 13.27 IRIC Setting Timing and SCL Control (3)........................................................... 324
Figure 13.28 Block Diagram of Noise Canceler ....................................................................... 325
Figure 13.29 Notes on Reading Master Receive Data............................................................... 331
Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission
Figure 13.31 Stop Condition Issuance Timing.......................................................................... 333
Figure 13.32 IRIC Flag Clear Timing on WAIT Operation...................................................... 334
Figure 13.33 IRIC Flag Clearing Timing When WAIT = 1 ...................................................... 334
Figure 13.34 ICDR Read and ICCR Access Timing in Slave Transmit Mode ......................... 335
Figure 13.35 TRS Bit Set Timing in Slave Mode ..................................................................... 336
Figure 13.36 Diagram of Erroneous Operation when Arbitration is Lost ................................. 337
Section 14 Keyboard Buffer Controller
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
Figure 14.5 (1) Sample Transmit Processing Flowchart.............................................................. 347
Receive Mode (MLS = WAIT = 0, HNDS = 1)................................................... 306
(Receiving Multiple Bytes) (WAIT = 1).............................................................. 307
(Receiving a Single Byte) (WAIT = 1) ................................................................ 308
(MLS = ACKB = 0, WAIT = 1) .......................................................................... 310
(MLS = ACKB = 0, WAIT = 1) .......................................................................... 311
(MLS = ACKB = 0, HNDS = 0) .......................................................................... 318
(MLS = ACKB = 0, HNDS = 0) .......................................................................... 318
and Timing........................................................................................................... 332
Block Diagram of Keyboard Buffer Controller ................................................... 339
Keyboard Buffer Controller Connection.............................................................. 340
Sample Receive Processing Flowchart ................................................................ 345
Receive Timing.................................................................................................... 346
Rev. 2.00 Mar 21, 2006 page xxxi of xxxviii