H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 347

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The reception procedure and operations using the wait function (WAIT bit), by which data is
sequentially received in synchronization with ICDR (ICDRR) read operations, are described
below.
The following describes the multiple-byte reception procedure. In single-byte reception, some
steps of the following procedure are omitted. At this time, follow the procedure shown in figure
13.14.
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
2. When ICDR is read (dummy data is read), reception is started, the receive clock is output in
3. The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been set to
4. Read the IRTR flag in ICSR.
5. If IRTR flag is 1, read ICDR receive data.
6. Clear the IRIC flag. When the flag is set as the first case in step [3], the master device outputs
Data can be received continuously by repeating steps [3] to [6].
7. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception.
8. After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first clock
9. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit value
10. Read the ICDR receive data.
11. Clear the IRIC flag to 0.
Clear the ACKB bit in ICSR to 0 to set the acknowledge data.
Clear the HNDS bit in ICXR to 0 to cancel the handshake function.
Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1.
synchronization with the internal clock, and data is received.
1, an interrupt request is sent to the CPU.
If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt reception.
the 9th clock and drives SDA low at the 9th receive clock pulse to return an acknowledge
signal.
pulse for the next receive data.
becomes valid when the rising edge of the next 9th clock pulse is input.
At the fall of the 8th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag clearing.
At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received. The master device outputs the receive clock continuously to receive the next data.
Rev. 2.00 Mar 21, 2006 page 309 of 518
Section 13 I
2
C Bus Interface (IIC)
REJ09B0299-0200