H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 373

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
12. Note on ICDR read and ICCR access in slave transmit mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
13. Note on TRS bit setting in slave mode
In I
during the time shaded in figure 13.34. However, such read and write operations cause no
problem in interrupt handling processing that is generated in synchronization with the rising
edge of the 9th clock pulse because the shaded time has passed before making the transition to
interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
In I
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 13.35), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 13.35), the bit value is suspended and remains invalid until the rising edge of the 9th
2
Read ICDR data that has been received so far or read/write from/to ICCR before starting
the receive operation of the next slave address.
Monitor the BC2 to BC0 bit counter in ICMR; when the count is 000 (8th or 9th clock
pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to
ICCR during the time other than the shaded time.
2
C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR
C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
ICXR.
ICXR.
Figure 13.34 ICDR Read and ICCR Access Timing in Slave Transmit Mode
TRS bit
SDA
SCL
Address reception
R/W
8
The rise of the 9th clock is detected
Waveform at problem occurrence
A
9
ICDR read and ICCR read/write are disabled
(6 system clock period)
Rev. 2.00 Mar 21, 2006 page 335 of 518
Section 13 I
ICDR write
Data transmission
2
C Bus Interface (IIC)
Bit 7
REJ09B0299-0200