H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 372

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 I
ASD
SCL
BC2–BC0
IRIC
(operation
example)
11. Note on IRIC flag clear when the wait function is used
Rev. 2.00 Mar 21, 2006 page 334 of 518
REJ09B0299-0200
If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be
inserted by driving the SCL pin low is used when the wait function is used in I
master mode, the IRIC flag should be cleared after determining that the SCL is low, as
described below.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in L’ state after the counter
value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 16.21.)
SDA
IRIC
SCL
A
2
C Bus Interface (IIC)
9
0
Figure 13.32 IRIC Flag Clear Timing on WAIT Operation
Figure 13.33 IRIC Flag Clearing Timing When WAIT = 1
1
7
IRIC flag clear available
SCL = low detected
VIH
2
6
Transmit/receive data
3
5
[1] SCL = low determination
4
Secures a high period
4
5
3
6
IRIC flag clear unavailable
2
7
1
[2] IRIC clear
8
SCL =
‘L’ confirm
IRIC flag clear available
0
A
IRIC clear
9
Transmit/receive
1
7
data
2
2
6
C bust interface
When BC2-0
IRIC clear
3
5
2