H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 179

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

An example of setting CFS to 1 (basic cycle = resolution (T)
output) is shown as an additional pulse. When CFS is set to 1, the duty ratio of the basic pulse is
determined by the upper eight bits (DA13 to DA6) in DADR, and the position of the additional
pulse is determined by the following six bits (DA5 to DA0) as shown in figure 8.5.
Tables 8.4 to 8.6 show the position of the additional pulse.
Here, the case of DADR = H'0207 (B'0000 0010 0000 0111) is considered. Figure 8.6 shows an
output waveform. Because CFS = 1 and the value of upper eight bits is B'0000 0010, the duty ratio
of the basic pulse is 2/256
DA13 DA12 DA11 DA10 DA9
Figure 8.4 Output Waveform (OS = 1, DADR Corresponds to T
t
t
t
H1
f1
H1
t
t
t
H1
Figure 8.5 D/A Data Register Configuration when CFS = 1
f1
H1
Basic pulse duty ratio
= t
+ t
= t
t
+ t
f1
f2
t
f1
H2
f2
H2
= t
= t
+ t
+ t
f3
f3
H3
= ··· = t
H3
= ··· = t
+ ··· + t
+ ··· + t
(T) of high width.
t
f255
H2
t
f63
H2
a. CFS = 0 [base cycle = resolution (T) × 64]
b. CFS = 1 [base cycle = resolution (T) × 256]
H255
DA8
H63
= t
= t
t
f2
t
f2
f64
f256
+ t
+ t
= T× 256
H64
H256
= T× 64
DA7
= T
= T
1 conversion cycle
1 conversion cycle
H
H
DA6
t
H3
t
H3
DA5
DA4
Rev. 2.00 Mar 21, 2006 page 141 of 518
Additional pulse position
t
H255
t
H63
Section 8 14-Bit PWM Timer (PWMX)
t
DA3
f255
t
256) and OS to 1 (PWMX inverted
f63
DA2
t
H256
t
DA1
H64
t
f256
t
f64
DA0
REJ09B0299-0200
H
)
CFS
1
1