H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 315

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.3.4
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit Bit Name
7
6
5
4
3
MLS
WAIT
CKS2
CKS1
CKS0
I
2
C Bus Mode Register (ICMR)
Initial Value R/W
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Wait Insertion Bit
This bit is valid only in master mode with the I
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8
the IRIC flag is set to 1 in ICCR, and a wait state begins
(with SCL at the low level). When the IRIC flag is cleared to
0 in ICCR, the wait ends and the acknowledge bit is
transferred.
For details, refer to section 13.4.7, IRIC Setting Timing and
SCL Control.
Transfer Clock Select 2 to 0
These bits are used only in master mode.
These bits select the required transfer rate, together with
the IICX1 (IIC_1) and IICX0 (IIC_0) bits in STCR. Refer to
table 13.3.
Rev. 2.00 Mar 21, 2006 page 277 of 518
Section 13 I
2
C bus format is used.
2
C Bus Interface (IIC)
REJ09B0299-0200
2
C bus
th
clock),