H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 349

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.4.5
In I
data, and the slave device returns an acknowledge signal.
The slave device operates as the device specified by the master device when the slave address in
the first frame following the start condition that is issued by the master device matches its own
address.
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 13.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1).
(master output)
(master output)
(slave output)
User processing
2
SCL
SDA
SDA
IRTR
ICDR
C bus format slave receive mode, the master device outputs the transmit clock and transmit
IRIC
Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode
Data 2
Slave Receive Operation
Bit 0
8
[4] IRTR = 0
[3]
Data 1
[6] IRIC clear
A
[4] IRTR = 1
[7] Set ACKB = 1
9
[8] Wait for one clock pulse
[3]
Bit 7
[9] Set TRS = 1
1
(MLS = ACKB = 0, WAIT = 1)
[10] ICDR read (Data 2)
Bit 6
2
Bit 5
3
Data 3
[11] IRIC clear
Bit 4
Data 2
4
Bit 3
5
Bit 2
6
Rev. 2.00 Mar 21, 2006 page 311 of 518
Bit 1
7
Bit 0
[14] IRIC clear
8
Section 13 I
[13] IRTR = 0
[12]
A
[15] WAIT cleared
[13] IRTR = 1
[12]
to 0, IRIC clear
9
[17] Stop condition
2
C Bus Interface (IIC)
REJ09B0299-0200
issuance
Data 3
Stop condition generation
[16] ICDR read
(Data 3)