H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 203

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
9.5.9
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. Figure 9.14 shows the OCRA write timing.
9.5.10
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a
signal that masks the ICRD input capture signal is generated. The mask signal is set by the input
capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the
OCRDM contents, and an FRC compare-match. Figure 9.15 shows the timing of setting the mask
signal. Figure 9.16 shows the timing of clearing the mask signal.
φ
FRC
OCRA
OCRAR, OCRAF
Compare-match
signal
φ
Input capture
signal
Input capture
mask signal
Automatic Addition Timing
Mask Signal Generation Timing
Figure 9.15 Timing of Input Capture Mask Signal Setting
Figure 9.14 OCRA Automatic Addition Timing
N
N
A
Section 9 16-Bit Free-Running Timer (FRT)
Rev. 2.00 Mar 21, 2006 page 165 of 518
N + A
N +1
REJ09B0299-0200

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