H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 313

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
13.3.3
SARX sets the second slave address and selects the communication format. If the LSI is in slave
mode with the I
match the upper 7 bits of the first frame received after a start condition, the LSI operates as the
slave device specified by the master device. SARX can be accessed only when the ICE bit in
ICCR is cleared to 0.
Bit Bit Name
7
6
5
4
3
2
1
0
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
Second Slave Address Register (SARX)
2
C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX
Initial Value R/W
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Second Slave Address 6 to 0
Set the second slave address.
Format Select X
Selects the communication format together with the FS bit
in SAR. Refer to table 13.2.
Rev. 2.00 Mar 21, 2006 page 275 of 518
Section 13 I
2
C Bus Interface (IIC)
REJ09B0299-0200

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