H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 91

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

3.2.3
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit
7
6
5
4
Bit Name
IICS
IICX1
IICX0
IICE
Serial Timer Control Register (STCR)
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
I
Specifies bits 7 to 4 of port A as output buffers
similar to SCL and SDA. These pins are used to
implement an I
0: PA7 to PA4 are normal input/output pins.
1: PA7 to PA4 are input/output pins enabling bus
driving.
I
These bits control the IIC operation. These bits
select a transfer rate in master mode together with
bits CKS2 to CKS0 in the I
(ICMR). For details on the transfer rate, refer to
table 13.3.
I
Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX
registers (DADRAH/DACR, DADRAL,
DADRBH/DACNTH, DADRBL/DACNTL), and SCI
registers (SMR, BRR, SCMR).
0: SCI_1 registers are accessed in an area from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
1: IIC_1 registers are accessed in an area from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
PWMX registers are accessed in an area from
H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to
H'(FF)FFA7.
IIC_0 registers are accessed in an area from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to
H'(FF)FFDF.
2
2
2
C Extra Buffer Select
C Transfer Rate Select 1 and 0
C Master Enable
Rev. 2.00 Mar 21, 2006 page 53 of 518
2
C interface only by software.
Section 3 MCU Operating Modes
2
C bus mode register
REJ09B0299-0200