H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 322

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 I
Bit Bit Name
1
Note: * Only 0 can be written, to clear the flag.
When, with the I
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag is not
set at the end of a data transfer up to detection of a retransmission start condition or stop condition
after a slave address (SVA) or general call address match in I
Tables 13.4 and 13.5 show the relationship between the flags and the transfer states.
Rev. 2.00 Mar 21, 2006 page 284 of 518
REJ09B0299-0200
IRIC
2
C Bus Interface (IIC)
2
C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
Initial Value R/W
0
R/(W) * Clocked synchronous serial format mode:
Description
When the ICDRE or ICDRF flag is set to 1 in any operating
mode:
[Clearing condition]
When 0 is written in IRIC after reading IRIC = 1
At the end of data transfer (rise of the 8th
transmit/receive)
When a start condition is detected
When a start condition is detected in transmit mode
(when a start condition is detected in transmit mode
and the ICDRE flag is set to 1)
When data is transferred among the ICDR register and
buffer (when data is transferred from ICDRT to ICDRS
in transmit mode and the ICDRE flag is set to 1, or
when data is transferred from ICDRS to ICDRR in
receive mode and the ICDRF flag is set to 1)
2
C bus format slave mode.