H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 410

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface LPC Interface (LPC)
Table 15.2 Register Selection
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
15.3.4
The IDR registers are 8-bit read-only registers for the slave processor (this LSI), and 8-bit write-
only registers for the host processor. The registers selected from the host according to the I/O
address are shown in the following table. For information on IDR3 selection, see section 15.3.3,
LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written
to the selected register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to
indicate whether the written information is a command or data. The initial values of IDR1 to IDR3
are undefined.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
0000 0000 0110
0000 0000 0110
Rev. 2.00 Mar 21, 2006 page 372 of 518
REJ09B0299-0200
Input Data Registers 1 to 3 (IDR1 to IDR3)
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
0
0
1
0
0
1
I/O Address
I/O Address
Bit 2
0
1
0
1
0
0
1
0
0
1
Bit 3
0
0
0
0
Bit 2
0
1
0
1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
0
0
1
0
0
1
Bit 1
0
0
1
1
0
0
Bit 0
0
0
0
1
1
0
1
1
Bit 0
0
0
0
0
Transfer Cycle Host Register Selection
I/O write
I/O write
I/O read
I/O read
I/O write
I/O write
I/O read
I/O read
Transfer Cycle
I/O write
I/O write
I/O write
I/O write
IDR3 write, C/D3
IDR3 write, C/D3
ODR3 read
STR3 read
TWR0MW write
TWR1 to TWR15 write
TWR0SW read
TWR1 to TWR15 read
Host Register Selection
IDR1 write, C/D1
IDR1 write, C/D1
IDR2 write, C/D2
IDR2 write, C/D2
0
1
0
1
0
1