H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 363

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.4.8
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 13.28 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
13.4.9
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 13.3.7, DDC Switch
Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
ICDRE and ICDRF internal flags
Transmit/receive sequencer and internal operating clock counter
Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
Noise Canceler
Initialization of Internal State
SCL or
SDA input
signal
Sampling
clock
D
Figure 13.28 Block Diagram of Noise Canceler
Sampling clock
System clock
cycle
Latch
C
Q
D
Latch
C
Q
Rev. 2.00 Mar 21, 2006 page 325 of 518
Section 13 I
detector
Match
2
C Bus Interface (IIC)
REJ09B0299-0200
Internal
SCL or
SDA
signal