H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 416

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface LPC Interface (LPC)
Bit
4
3
2
1
Rev. 2.00 Mar 21, 2006 page 378 of 518
REJ09B0299-0200
Bit Name Initial Value Slave Host Description
SWMF
C/D3
DBU32
IBF3A
0
0
0
0
R/(W) * R
R
R/W
R
R/W
R
R
R
Slave Write Mode Flag
Set to 1 when the slave processor (this LSI) writes to
TWR0. In the event of simultaneous writes by the
master and the slave, the master write has priority.
SWMF is cleared to 0 when the host reads TWR15
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
SWMF bit
1: [Setting condition]
When the slave processor writes to TWR0 while
MWMF = 0
Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
Defined by User
The user can use this bit as necessary.
Input Buffer Full
Set to 1 when the host processor writes to IDR. This
bit is an internal interrupt source to the slave
processor (this LSI). IBF is cleared to 0 when the
slave processor reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details,
see table 15.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle