H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 177

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 8.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the
resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR
contains at least a certain minimum value.
Table 8.3
Note: * This column indicates the conversion cycle when specific DADR bits are fixed.
CKS
0
1
Resolu
tion T (µs) CFS
0.1
0.2
Settings and Operation (Examples When = 10 MHz)
0
1
0
1
Base
Cycle (µs)
6.4
25.6
12.8
51.2
Conversion
Cycle (µs)
1638.4
3276.8
T
T
1. Always low (or high)
2. (Data value)
1. Always low (or high)
2. (Data value)
1. Always low (or high)
2. (Data value)
1. Always low (or high)
2. (Data value)
L
H
(DADR = H'0001 to
H'03FD)
(DADR = H'0401 to
H'FFFD)
(DADR = H'0003 to
H'00FF)
(DADR = H'0103 to
H'FFFF)
(DADR = H'0001 to
H'03FD)
(DADR = H'0401 to
H'FFFD)
(DADR = H'0003 to
H'00FF)
(DADR = H'0103 to
H'FFFF)
(if OS = 0)
(if OS = 1)
Rev. 2.00 Mar 21, 2006 page 139 of 518
Section 8 14-Bit PWM Timer (PWMX)
T
T
T
T
Fixed DADR Bits
Accuracy
(Bits)
14
12
10
14
12
10
14
12
10
14
12
10
Bit Data
3 2 1 0
0 0 0 0 102.4
0 0 0 0 102.4
0 0 0 0 204.8
0 0 0 0 204.8
REJ09B0299-0200
0 0 409.6
0 0 409.6
0 0 819.2
0 0 819.2
Conversion
Cycle * (µs)
1638.4
1638.4
3276.8
3276.8