H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 245

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
WDT0102B_000020020800
This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer
can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents
the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can
output an overflow signal (RESO) externally.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows. A block
diagram of the WDT_0 and WDT_1 is shown in figure 11.1.
11.1
Watchdog Timer Mode:
Interval Timer Mode:
Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks.
Switchable between watchdog timer mode and interval timer mode
If the counter overflows, an internal reset or an internal NMI interrupt is generated.
When the LSI is selected to be internally reset at counter overflow, a low level signal is output
from the RESO pin if the counter overflows.
If the counter overflows, an interval timer interrupt (WOVI) is generated.
Features
Section 11 Watchdog Timer (WDT)
Rev. 2.00 Mar 21, 2006 page 207 of 518
Section 11 Watchdog Timer (WDT)
REJ09B0299-0200

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