H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 172

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 14-Bit PWM Timer (PWMX)
8.3.2
DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. Since
DADR consists of 16-bit data, DADR transfers data to the CPU via the temporary register
(TEMP). For details, refer to section 8.4, Bus Master Interface.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rev. 2.00 Mar 21, 2006 page 134 of 518
REJ09B0299-0200
DADRA
Bit Name
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
CFS
—
PWM (D/A) Data Registers A and B (DADRA, DADRB)
Initial Value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by
keeping the two lowest data bits (DA1 and DA0) cleared
to 0. The two lowest data bits correspond to the two
highest bits in DACNT.
Carrier Frequency Select
0: Base cycle = resolution (T)
DADR range = H'0401 to H'FFFD
1: Base cycle = resolution (T)
DADR range = H'0103 to H'FFFF
Reserved
This bit is always read as 1 and cannot be modified.
64
256