H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 376

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 13 I
13.6.1
The IIC operation can be enabled or disabled using the module stop control register. The initial
setting is for the IIC operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 19, Power-Down Modes.
Rev. 2.00 Mar 21, 2006 page 338 of 518
REJ09B0299-0200
address does not match. Similarly, if the start condition or address is transmitted from the
master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag
is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt
source even when the address does not match.
To use the I
A. When having received 1 as the acknowledge bit value for the last transmit data at the end
B. Set receive mode (TRS = 0) before the next start condition is input in slave mode.
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
Complete transmit operation by the procedure shown in figure 13.23, in order to switch
from slave transmit mode to slave receive mode.
Module Stop Mode Setting
2
C Bus Interface (IIC)
2
C bus interface module in slave mode, be sure to follow the procedures below.

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