H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 465

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

17.8.2
When erasing flash memory, the erase/erase-verify flowchart shown in figure 17.10 should be
followed.
1. Prewriting (setting erase block data to all 0) is not necessary.
2. Erasing is performed in block units. Make only a single-block specification in erase block
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as
registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in
turn.
An overflow cycle of approximately (y + z +
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
before. The maximum number of repetitions of the erase/erase-verify sequence is N.
Erase/Erase-Verify
+
ms is allowed.
Rev. 2.00 Mar 21, 2006 page 427 of 518
REJ09B0299-0200
Section 17 ROM