H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 442

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface LPC Interface (LPC)
Table 15.9 summarizes the methods of setting and clearing these bits, and Figure 15.8 shows the
processing flowchart.
Table 15.9 HIRQ Setting and Clearing Conditions
Host Interrupt
HIRQ1
(independent
from IEDIR)
HIRQ12
(independent
from IEDIR)
SMI
(IEDIR = 0)
SMI
(IEDIR = 1)
HIRQi
(i = 6, 9 to 11)
(IEDIR = 0)
HIRQi
(i = 6, 9 to 11)
(IEDIR = 1)
Rev. 2.00 Mar 21, 2006 page 404 of 518
REJ09B0299-0200
Setting Condition
Internal CPU writes to ODR1, then reads
0 from bit IRQ1E1 and writes 1
Internal CPU writes to ODR1, then reads
0 from bit IRQ12E1 and writes 1
Internal CPU
Internal CPU
Internal CPU
Internal CPU
writes to ODR2, then reads 0 from bit
SMIE2 and writes 1
writes to ODR3, then reads 0 from bit
SMIE3A and writes 1
writes to TWR15, then reads 0 from
bit SMIE3B and writes 1
reads 0 from bit SMIE2, then writes 1
reads 0 from bit SMIE3A, then writes
1
reads 0 from bit SMIE3B, then writes
1
writes to ODR2, then reads 0 from bit
IRQiE2 and writes 1
writes to ODR3, then reads 0 from bit
IRQiE3 and writes 1
reads 0 from bit IRQiE2, then writes 1
reads 0 from bit IRQiE3, then writes 1
Clearing Condition
Internal CPU writes 0 to bit IRQ1E1,
or host reads ODR1
Internal CPU writes 0 to bit IRQ12E1,
or host reads ODR1
Internal CPU
Internal CPU
Internal CPU
Internal CPU
writes 0 to bit SMIE2, or host
reads ODR2
writes 0 to bit SMIE3A, or host
reads ODR3
writes 0 to bit SMIE3B, or host
reads TWR15
writes 0 to bit SMIE2
writes 0 to bit SMIE3A
writes 0 to bit SMIE3B
writes 0 to bit IRQiE2, or host
reads ODR2
CPU writes 0 to bit IRQiE3, or
host reads ODR3
writes 0 to bit IRQiE2
writes 0 to bit IRQiE3