H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 75

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 2.10 Block Data Transfer Instructions
Instruction
EEPMOV.B
EEPMOV.W
2.6.2
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
Register field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.
Effective address extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
Condition field
Specifies the branching condition of Bcc instructions.
Basic Instruction Formats
Size
—
—
Function
if R4L
else next;
if R4
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
Repeat @ER5 +
Until R4L = 0
Repeat @ER5 +
Until R4 = 0
0 then
0 then
R4L–1
R4–1
R4
R4L
@ER6+
@ER6+
Rev. 2.00 Mar 21, 2006 page 37 of 518
REJ09B0299-0200
Section 2 CPU