H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 22

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3 Register Descriptions ........................................................................................................ 223
12.4 Operation in Asynchronous Mode .................................................................................... 237
12.5 Multiprocessor Communication Function......................................................................... 248
12.6 Operation in Clocked Synchronous Mode ........................................................................ 254
12.7 Interrupt Sources............................................................................................................... 262
12.8 Usage Notes ...................................................................................................................... 263
Rev. 2.00 Mar 21, 2006 page xxii of xxxviii
12.3.1 Receive Shift Register (RSR) .............................................................................. 223
12.3.2 Receive Data Register (RDR) .............................................................................. 224
12.3.3 Transmit Data Register (TDR)............................................................................. 224
12.3.4 Transmit Shift Register (TSR) ............................................................................. 224
12.3.5 Serial Mode Register (SMR)................................................................................ 225
12.3.6 Serial Control Register (SCR).............................................................................. 227
12.3.7 Serial Status Register (SSR) ................................................................................ 229
12.3.8 Serial Interface Mode Register (SCMR).............................................................. 231
12.3.9 Bit Rate Register (BRR) ...................................................................................... 232
12.3.10 Serial Pin Select Register (SPSR) ........................................................................ 237
12.4.1 Data Transfer Format........................................................................................... 238
12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 239
12.4.3 Clock.................................................................................................................... 240
12.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 241
12.4.5 Data Transmission (Asynchronous Mode)........................................................... 242
12.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 244
12.5.1 Multiprocessor Serial Data Transmission ............................................................ 250
12.5.2 Multiprocessor Serial Data Reception ................................................................. 251
12.6.1 Clock.................................................................................................................... 254
12.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 255
12.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 256
12.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 258
12.6.5 Simultaneous Serial Data Transmission and Reception
12.8.1 Module Stop Mode Setting .................................................................................. 263
12.8.2 Break Detection and Processing .......................................................................... 263
12.8.3 Mark State and Break Detection .......................................................................... 263
12.8.4 Receive Error Flags and Transmit Operations
12.8.5 Relation between Writing to TDR and TDRE Flag ............................................. 263
12.8.6 SCI Operations during Mode Transitions ............................................................ 264
12.8.7 Switching from SCK Pins to Port Pins ................................................................ 267
(Clocked Synchronous Mode) ............................................................................. 260
(Clocked Synchronous Mode Only) .................................................................... 263