H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 407

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
4
3
2
Bit Name Initial Value Slave Host Description
ABRT
IBFIE3
IBFIE2
0
0
0
R/W
R/(W) * —
R/W
R/W
—
—
LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle
Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
1: [When TWRIE = 0 in LADR3]
IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register (IDR2) receive completed
1: Input data register (IDR2) receive completed
IDR3 and TWR Receive Completion Interrupt
completed interrupt requests disabled
interrupt requests disabled
interrupt requests enabled
Writing 0 after reading ABRT = 1
LPC hardware reset and LPC software reset
LPC hardware shutdown and LPC software
shutdown
Input data register (IDR3) receive completed
interrupt requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive
completed interrupt requests enabled
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 369 of 518
REJ09B0299-0200