H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 126

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
5.8.2
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.8.3
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
5.8.4
According to the pin status after a reset, IRQnF may be set to 1, so ISR should be read after a reset
to write 0. (n = 7 to 0)
Rev. 2.00 Mar 21, 2006 page 88 of 518
REJ09B0299-0200
L1:
Instructions that Disable Interrupts
Interrupts during Execution of EEPMOV Instruction
IRQ Status Register (ISR)
EEPMOV.W
MOV.W
BNE
R4,R4
L1