H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 366

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 I
Table 13.8 I
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Note: * 6t
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
5. The I
Table 13.9 Permissible SCL Rise Time (t
IICX
0
1
Rev. 2.00 Mar 21, 2006 page 328 of 518
REJ09B0299-0200
therefore depends on the system clock cycle t
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 13.9.
2
t
7.5 t
17.5 t
cyc
C bus interface specification for the SCL rise time t
cyc
when IICX is 0, 12t
Indication
2
cyc
C Bus Interface (IIC)
2
cyc
C Bus Timing (SCL and SDA Outputs)
Standard mode
High-speed mode
Standard mode
High-speed mode
cyc
when 1.
2
C bus interface AC timing specifications will not be met with a
2
C bus interface monitors the SCL line and synchronizes
Time Indication
I
(Max.)
1000
300
1000
300
2
Symbol Output Timing
t
t
t
t
t
t
t
t
t
C Bus Specification
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
sr
) Values
sr
(the time for SCL to go from low to V
cyc
2
C bus interface, the high period of SCL is
, as shown in section 21, Electrical
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
3t
SCLO
SCLLO
SCLL
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
– (6t
to 256t
[ns]
– 3t
– 1t
– 1t
+ 2t
sr
cyc
cyc
is 1000 ns or less (300 ns for high-
cyc
cyc
cyc
or 12t
cyc
5 MHz
1000
300
1000
300
=
cyc
* )
8 MHz
300
300
937
1000
Unit
ns
=
Notes
See figure
21.21.
IH
10 MHz
750
300
1000
300
) exceeds
=