H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 52

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 2 CPU
2.1.1
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Instruction
MULXU
MULXS
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
Rev. 2.00 Mar 21, 2006 page 14 of 518
REJ09B0299-0200
High-speed operation
All frequently-used instructions are executed in one or two states
8/16/32-bit register-register add/subtract: 1 state
8
16
16
32
Two CPU operating modes
Normal mode
Advanced mode
Power-down state
Transition to power-down state by SLEEP instruction
Selectable CPU clock speed
Register configuration
The MAC register is supported only by the H8S/2600 CPU.
Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
The number of execution states of the MULXU and MULXS instructions
8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
8-bit register-register divide: 12 states (DIVXU.B)
16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
16-bit register-register divide: 20 states (DIVXU.W)
Differences between H8S/2600 CPU and H8S/2000 CPU
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
H8S/2600
3
4
4
5
Execution States
H8S/2000
12
20
13
21

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