H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 475

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Table 18.4 External Clock Output Stabilization Delay Time
Condition: V
Note: * t
18.2
The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects
the duty of a clock that is output from the oscillator, and generates the system clock ( ).
18.3
The medium-speed clock divider divides the system clock ( ), and generates /2, /4, /8, /16,
and /32 clocks.
Item
External clock output stabilization delay
time
DEXT
Note:* The external clock output stabilization delay time (t
V
STBY
EXTAL
φ
(Internal and external)
RES
Duty Correction Circuit
Medium-Speed Clock Divider
CC
Figure 18.6 Timing of External Clock Output Stabilization Delay Time
includes a RES pulse width (t
CC
2.7 V
= 2.7 V to 3.6 V, V
V
IH
SS
= 0 V
Symbol
t
RESW
DEXT
*
).
t
DEXT
*
Min.
500
DEXT
) includes a RES pulse width (t
Rev. 2.00 Mar 21, 2006 page 437 of 518
Section 18 Clock Pulse Generator
Max.
Unit
s
RESW
REJ09B0299-0200
).
Remarks
Figure 18.6

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