H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 191

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.3.7
TCSR is used for counter clear selection and control of interrupt request signals.
Bit
Bit
2
1
0
7
Bit Name
Bit Name
OCIBE
OVIE
—
ICFA
Timer Control/Status Register (TCSR)
Initial Value
Initial Value
0
0
1
0
R/W
R/W
R/W
R/W
R
R/(W) * Input Capture Flag A
Description
This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture
signal. When BUFEA = 1, ICFA indicates that the old
ICRA value has been moved into ICRC and the new
FRC value has been transferred to ICRA. Only 0 can be
written to this bit to clear the flag.
[Setting condition]
When an input capture signal causes the FRC value to
be transferred to ICRA
[Clearing condition]
Read ICFA when ICFA = 1, then write 0 to ICFA
Description
Output Compare Interrupt B Enable
Selects whether to enable output compare interrupt B
request (OCIB) when output compare flag B (OCFB) in
TCSR is set to 1.
0: OCIB requested by OCFB is disabled
1: OCIB requested by OCFB is enabled
Timer Overflow Interrupt Enable
Selects whether to enable a free-running timer overflow
request interrupt (FOVI) when the timer overflow flag
(OVF) in TCSR is set to 1.
0: FOVI requested by OVF is disabled
1: FOVI requested by OVF is enabled
Reserved
This bit is always read as 1 and cannot be modified.
Section 9 16-Bit Free-Running Timer (FRT)
Rev. 2.00 Mar 21, 2006 page 153 of 518
REJ09B0299-0200