AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 141

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AU80610004653AAS LBMG

Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet

Specifications of AU80610004653AAS LBMG

Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Processor Configuration Registers
1.9.26
1.9.27
Datasheet
15:8
6:4
Bit
7
Access
HSRW - Hardware Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
MC - Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
System software can modify bits in this register, but the device is prohibited from doing
so. If the device writes the same message multiple times, only one of those messages
is guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
RW
RO
RO
15:0
Bit
Default
Value
000b
Access
00h
0b
RW
RST/PWR
FLR, Core
Default Value
Core
Core
0000h
Reserved
64 Bit Capable (64BCAP):
Hardwired to 0 to indicate that the function does not
implement the upper 32 bits of the Message address
register and is incapable of generating a 64-bit memory
address.
This may need to change in future implementations when
addressable system memory exceeds the 32b/4GB limit.
Multiple Message Enable (MME):
System software programs this field to indicate the actual
number of messages allocated to this device. This
number will be equal to or less than the number actually
requested.
The encoding is the same as for the MMC field below.
0/2/0/PCI
60-61h
0000h
16 bits
0/2/0/PCI
92-93h
0000h
16 bits
RW;
RO; RW;
RST/PWR
FLR, Core
Reserved R/W
Description
Description
141

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