AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 50
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.5.19
50
For these reasons the following critical restriction is placed on the programming of the
PAM regions: At the time that a DMI accesses to the PAM region may occur, the
targeted PAM segment must be programmed to be both readable and writeable.
PAM1 - Programmable Attribute Map 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0C0000h- 0C7FFFh.
This register controls the read, write, and shadowing attributes of the BIOS areas from
7:6
5:4
3:0
7:6
Bit
Bit
Access
Access
RW-L
RO
RO
RO
Default
Default
Value
Value
00b
00b
00b
0h
0/0/0/PCI
91h
00h
8 bits
RO; RW-L;
RST/
RST/
PWR
PWR
Core
Core
Core
Core
Reserved
0F0000-0FFFFF Attribute
(HIENABLE):
and write cycles that address the BIOS
area from 0F0000 to 0FFFFF.
00: DRAM Disabled: All accesses are
directed to DMI.
01: Read Only: All reads are sent to
DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to
DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads
and writes are serviced by DRAM.
Reserved
Reserved
This field controls the steering of read
Processor Configuration Registers
Description
Description
Datasheet
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