AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 44
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.5.14
44
15:10
9:8
7:4
3:2
Bit
Access
RW-L
RW-L
RO
RO
GGC - Processor Graphics Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Default
Value
0011b
00h
00b
0h
RST/
PWR
Core
Core
Core
Core
Reserved
GTT Graphics Memory Size (GGMS):
This field is used to select the amount of Main Memory that is pre-
allocated to support the Internal Graphics Translation Table. The
BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled.
00: No memory pre-allocated. GTT cycles (Mem and IO) are not
claimed.
01: 1 MB of memory pre-allocated for GTT.
10: Reserved
11: Reserved
NOTE: This register is locked and becomes Read Only when the
Graphics Mode Select (GMS):
This field is used to select the amount of Main Memory that is pre-
allocated to support the Internal Graphics device in VGA (non-
linear) and Native (linear) modes. The BIOS ensures that memory
is pre-allocated only when Internal graphics is enabled.
NOTE:
1.
2.
Reserved
0000
0001
0011
Others
D_LCK bit
This register is locked and becomes Read Only when the
D_LCK bit or MSLOCK in the SMRAM register is set.
BIOS Requirement: BIOS must not set this field to 000 if
IVD (bit 1 of this register) is 0.
No memory pre-allocated. Device 2
(IGD) does not claim VGA cycles
(Mem and IO), and the Sub-Class
Code field within Device 2 function 0
Class Code register is 80.
DVMT (UMA) mode, 1 MB of memory
pre-allocated for frame buffer.
DVMT (UMA) mode, 8 MB of memory
pre-allocated for frame buffer.
Reserved
0/0/0/PCI
52-53h
0030h
RW-L; RO
16 bits
or MSLOCK
Description
Processor Configuration Registers
in the SMRAM register is set.
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