AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 36

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.4
36
PCISTS - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This status register reports the occurrence of error events on Device 0's PCI interface.
Since the processor Device 0 does not physically reside on PCI_A many of the bits are
not implemented.
Bit
15
14
13
12
11
Access
RWC
RWC
RWC
RWC
RO
Default
Value
0b
0b
0b
0b
0b
0/0/0/PCI
6-7h
0090h
16 bits
RWC; RO;
(Sheet 1 of 2)
RST/
PWR
Core
Core
Core
Core
Core
Detected Parity Error (DPE):
This bit is set when this Device receives a
Poisoned TLP.
Signaled System Error (SSE):
This bit is set to 1 when the processor
Device 0 generates an SERR message
over DMI for any enabled Device 0 error
condition. Device 0 error conditions are
enabled in the PCICMD, ERRCMD, and
DMIUEMSK registers. Device 0 error flags
are read/reset from the PCISTS, ERRSTS,
or DMIUEST registers. Software clears
this bit by writing a 1 to it.
Received Master Abort Status
(RMAS):
generates a DMI request that receives an
Unsupported Request completion packet.
Software clears this bit by writing a 1 to
it.
Received Target Abort Status
(RTAS):
This bit is set when the processor
generates a DMI request that receives a
Completer Abort completion packet.
Software clears this bit by writing a 1 to
it.
Signaled Target Abort Status (STAS):
The processor will not generate a Target
Abort DMI completion packet or Special
Cycle. This bit is not implemented in the
processor and is hardwired to a 0. Writes
to this bit position have no effect.
This bit is set when the processor
Processor Configuration Registers
Description
Datasheet