AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 76
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.6.2
76
15:10
1:0
9:0
Bit
Bit
Access
Access
RW-L
C0DRB0 – Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Boundary Registers define the upper boundary address of each DRAM
rank with a granularity of 64MB. Each rank has its own single-word DRB register. These
registers are used to determine which chip select will be active for a given address.
Channel and rank map:
RO
RO
ch0 rank0:200h
ch0 rank1:202h
ch0 rank2:204h
ch0 rank3:206h
000000b
Default
Default
Value
Value
000h
00b
RST/
RST/
PWR
PWR
Core
Core
Core
Reserved
Reserved
Channel 0 Dram Rank Boundary Address 0
(C0DRBA0):
This register defines the DRAM rank boundary for rank0
of Channel 0 (64 MB granularity)
=R0
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
0/0/0/MCHBAR
200-201h
0000h
16 bits
RO; RW-L;
Processor Configuration Registers
Description
Description
Datasheet
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